1. Field of the Invention
The present invention relates generally to electronic circuits and methods and, in particular, to a high speed current mirror circuit for use, by way of example, as an active amplifier load.
2. Description of Related Art
Amplifier circuits commonly use active loads, as compared to passive or resistive loads, for the purpose of increased gain together with low voltage operation. Current mirrors are a common type of active load. Referring to the drawings, FIG. 1 is a schematic diagram of a buffer circuit which utilizes a differential amplifier 10. As will be explained, amplifier 10 includes a conventional current mirror active load.
FIG. 2 is a simplified diagram of the FIG. 1 buffer circuit showing that the amplifier 10 is configured as a voltage follower circuit with the output connected directly back to the inverting input. In a typical application, amplifier 10 is used to buffer the output of a reference voltage circuit (not depicted) so that the fixed reference voltage generated by the reference circuit can be utilized by other local circuits. Buffering is required since the local circuits may introduce noise onto the reference circuit thereby corrupting the circuit.
Amplifier 10 includes N type transistors 12A and 12B which form a differential transistor pair having their sources connected to a common tail current source 20. Source 20 produces a relatively constant output current I.sub.B. A pair of cascode connected N type transistors 14A and 14B is connected to input transistors 12A and 12B and have their gates connected to a bias voltage V.sub.BN. As is well known, transistors 14A and 14B operate to increase the effective impedance seen by the active load thereby increasing the voltage gain of the amplifier.
The active load includes P type transistor pair 18A and 18B which have their gates connected to a common bias voltage point. As will be explained, transistors 18A and 18B function together as a current mirror, with the nominal currents in the transistors being equal. The active load further includes cascode connected transistors 16A and 16B having their gates connected to a bias voltage source VBP. Transistors 16A and 16B operate to increase the output impedance of the active load thereby increasing the amplifier gain.
As is well known, when an MOS transistor is biased to operate in the saturation region, the drain-source current is proportional to the aspect ratio of the transistor, that is, the ratio of channel width to channel length (W/L). If two matched transistors operating in the saturation region are biased at the same point, the ratio of the relative current magnitudes will be the same as the ratio of the two aspect ratios. For transistors implemented in a common integrated circuit, such transistors usually have the same channel length L so that channel aspect ratio is controlled by changing the effective channel width W.
Transistors 18A and 18B are matched devices having the same geometry and the same gate-source voltage. In addition, the steady state drain-source voltages of the two transistors are the same due to the action of transistors 16A and 16B. Transistors 18A and 18B thus operate as a high precession current mirror, with the current I.sub.B produced by current source 20 being split equally between the two transistors. The biasing of transistors 18A and 18B insures that the drain-source voltage is greater than the difference between the threshold voltage of the transistors and the gate-source voltage so that the two transistors operate in the saturation region, a requirement for achieving high gain. If the drain-source voltage is smaller than the difference between the gate-source voltage and the threshold voltage, the transistor will operate in the triode (linear) region and will have a impedance significantly smaller than the impedance achieved when operating in the saturation region.
The output of amplifier 10 is at the node intermediate transistors 14B and 16B and is connected directly to the gate of transistor 12B which forms the inverting amplifier input. The node intermediate transistors 16A and 14A is connected to the gates of transistors 18A and 18B, with this connection providing feedback which biases transistors 18A and 18B at the proper level.
In order to maximize the available voltage swing of the output Out, bias voltage V.sub.BP is made as close as possible to the supply voltage V.sub.DD. However, voltage V.sub.BP must be sufficiently small to ensure that the drain-source voltage across transistors 18A and 18B is large enough for transistors 18A and 18B to be in the saturation region. The available voltage swing is further enhanced by making transistors 16A and 16B large (wide channel) to keep the required saturation voltage as small as possible.
Since amplifier 10 has only a single stage, the transient response of the single pole system is very fast for the amount of current required. However, when transistors 16A and 16B are made large for the reason previously noted, the parasitic capacitances of the transistors cause the associated non-dominant poles to adversely affect the transient response. As a result, ringing appears in the output as the amplifier attempts to recover from the dynamic disturbances introduced by the local circuits connected to the amplifier output.
The present invention overcomes the above-noted shortcomings of the prior art. A current mirror circuit suitable of use as an active amplifier load permits low voltage operation while providing high gain, wide voltage swing and improved transient response. These and other advantages of the present invention will become apparent to those skilled in the art based upon a reading of the following Detailed Description of the Invention.